Since various kinds of current consumptive electronic products such as a communication device (e.g. a mobile phone), an image-capturing device, a storage device and a networking device are almost developed in a tendency of multiple functions, i.e. a high definition, a high density or a high storage volume, this brings a demand on instantly processing a huge amount of digital contents. For convenience of the user on rapidly transmitting a huge amount of digital contents between a host and its peripheral devices, most of said consumptive electronic products are disposed with a widely-used high-speed serial bus transmission architecture including, for example, an universal serial bus (USB) or an IEEE1394 interface transmission architecture.
In the current USB interface data transmission architecture, the last standard specification of the USB has been developed to 3.0 version. USB 3.0 version is not only compatible with USB 2.0 version to own most of the original functions of USB 2.0 (e.g. retaining a micro-frame timer range of 125 microseconds) but also provides an operation with a super-speed data transmission speed of up to 5 Gbps, which is faster over 10 times than the highest data transmission speed 480 Mbps of a high-speed or full-speed USB 2.0 version. However, under this manner, a super-speed signal transmission of USB 3.0 has a lower tolerable frequency error with relative to a high-speed or full-speed signal transmission of USB 2.0.
Referring to FIG. 1, a conventional USB interface data transmission architecture is shown, which includes a USB 2.0-standardized host 10 and a USB 2.0/3.0-standardized device 12 connected with the host 10 via corresponding USB interfaces for transmitting a high-speed or full-speed USB 2.0-standardized signal therebetween. Since the signal transmission frequency resolution required for the USB interface is very high, a USB control chip of the USB device 12 needs to employ an external crystal oscillator 14 for generating a clock frequency to be a working frequency thereof. However, the usage of the external crystal oscillator 14 does not only cost higher but also invokes occurrence of a frequency error problem in the working frequency in comparison with a USB 2.0-standardized input signal transmitted from the USB host 10. Assuming another manner that the USB host 10 and USB device 12 both are standardized in USB 3.0 version specification, a tolerable frequency error needed for the USB device 12 receiving the super-speed transmission signal of USB 3.0 is lower than needed for the USB device 12 receiving a high-speed or full-speed transmission signal of USB 2.0. It means that the demand on a clock frequency resolution of the super-speed transmission signal of USB 3.0 is higher.
Furthermore referring to FIG. 2, which shows another conventional USB interface data transmission architecture disclosed in TW Patent Pub. No. 200719154 (as thereafter referred to Patent Pub. No. '154) including a USB host 20 and a USB device 22 connected with each other for transmitting USB signal therebetween. As shown in FIG. 2 of Patent Pub. No. '154, the USB device needs to additionally employ a frequency signal source 24 (referring to a reference clock generating circuit 132 disclosed in FIG. 7 of Patent Pub. No. '154) to provide a reference clock signal according to a corrected output signal. Then, a frequency synthesizer (as referring to a phase-locked loop 134 disclosed in FIG. 7 of Patent Pub. No. '154) is used to calibrate a working frequency according to the reference clock signal. However, such a conventional circuit design is highly complicated and costs higher. For USB transmission signal, the working frequency calibrated by the frequency signal source generated from the reference clock generating circuit still has the inaccurate frequency resolution problem. Specially, if the USB host 20 and USB device 22 both are standardized in USB 3.0 version specification, the demand on a clock frequency resolution of the super-speed transmission signal of USB 3.0 is greatly higher.